About Cache Miss Rate
The Cache Miss Rate is a critical performance metric in computer architecture and software engineering. It represents the fraction of memory accesses that are not found in the cache (L1, L2, or L3) and must be retrieved from a lower level of the memory hierarchy, such as main RAM or disk storage.
A high miss rate indicates that the CPU is frequently stalling while waiting for data, significantly increasing the Average Memory Access Time (AMAT) and reducing overall system performance.
The Formulas
To evaluate cache efficiency, we use two primary formulas:
Why is Miss Rate Important?
- Latency: Accessing main memory can be 100x slower than accessing the L1 cache. Minimizing misses keeps the CPU fed with instructions and data.
- Power Consumption: Fetching data from off-chip DRAM consumes significantly more energy than reading from on-chip SRAM.
- Throughput: In high-performance computing, the bottleneck is often memory bandwidth. Reducing the miss rate reduces the pressure on the memory bus.
Types of Cache Misses (The 3 Cs)
When optimizing code to reduce the miss rate calculated above, engineers look at three categories:
- Compulsory Misses: Occur during the first access to a block. The block has never been in the cache before.
- Capacity Misses: Occur when the cache cannot contain all the blocks needed during execution of a program.
- Conflict Misses: Occur in set-associative or direct-mapped caches when multiple blocks compete for the same set.
Example Calculation
Suppose a CPU executes a program that requires 500,000 memory accesses. During execution, the performance counters record 12,500 cache misses.
Miss Rate = 12,500 / 500,000 = 0.025 or 2.5%
Hit Rate = 1 – 0.025 = 0.975 or 97.5%